Integrated circuit devices typically display sensitivity to electrostatic discharge (ESD) events thus making it necessary to take measures to protect these circuits. The I/O circuits may be self-protecting by making them more robust so as to be capable of handling the high ESD currents.
In the case of BiCMOS technology, self-protecting I/O circuits are commonly implemented as BJT structures. A typical BJT structure is shown in FIGS. 1 and 2. In FIG. 1, the npn BJT 100 is shown in cross-section to show the p-base 102 formed in a p-substrate 104. The collector 106, comprising n+ region 108, n− sinker 110, and n-buried layer (NBL) 112, is also formed in the p-substrate 104. The BJT 100, further, includes an emitter 114 in the form of a polysilicon region. FIG. 1 also shows two base contacts 120 and a collector contact 122 Shallow trench isolation (STI) regions 130, 132 isolate the device from other devices and STI 134 separates the collector 106 from the emitter 114 to limit junction breakdown. It will be appreciated that process variations may result in slight structural variations in defining the emitter, base and collector regions.
While BJTs provide the necessary drive for the output circuit during normal operation, and snapback under ESD conditions, they do not necessarily trigger at the desired voltage during snapback.
The major alternative to BJTs is the use of SCR-like structures, which display higher ESD efficiency. In order to incorporate SCR characteristics into a BJT structure, a p+ region 350 acting as an SCR emitter, is included in the BJT structure to define a Bipolar SCR as shown in FIGS. 3 and 4. The structure remains pretty much the same as the BJT shown in FIGS. 1 and 2, with p-base 302 formed in a p-substrate 304. The collector 306, comprising n+ region 308, n− sinker 310, and n-buried layer (NBL) 312, is also formed in the p-substrate 304. The Bipolar SCR structure 300 also includes an emitter 314 in the form of a polysilicon region. It also includes two base contacts 320 and a collector contact 322. Shallow trench isolation (STI) regions 330, 332 isolate the device from other devices and STI 334 separates the BJT collector 306 from the BJT emitter 314. The SCR emitter 350, which has been added, is contacted by a contact 352, which is shown in FIG. 3 and is connected to the contact 322 of the collector 306. The device of FIGS. 3 and 4 provides for two stage triggering operation. Initially the BJT structure is triggered after avalanche breakdown of the blocking junction. This results in a high avalanche injection current which biases the p+ region 350, thereby paving the way for the injection of holes and the creation of a high density electron-hole plasma. This reduces the electric field below the breakdown level.
However, for high speed devices such as certain Si—Ge BiCMOS devices, the Bipolar SCR (BSCR) discussed above, cannot be used. These high speed devices have a thin epitaxial layer (of the order of 0.5 μm) to reduce collector resistance and thus the transient time at high frequencies such as microwave. The epitaxial layer is grown on top of the n-buried layer (NBL), and forms the medium on which and in which subsequent regions are formed In order to define the emitter 314, the shallow trench isolation region 334 is formed, which extends substantially to the depth of the epitaxial region. This provides good collector isolation from lateral current transport and is necessary to support with the high speed requirements. As a result, any p+ region on the anode side (such as the p+ region 350) becomes very well isolated since the STI between anode and cathode (STI 334 in FIG. 3), which is a necessary part of the emitter self-align process, extends to or below the level of the shallow NBL. The isolation of the p+ region essentially has the effect of eliminating it from the functionality of the device, which therefore behaves simply as a BJT.
The present invention provides a structure and method for providing a BSCR that is useable for high speed and other shallow NBL devices.